| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 1 | Realization of Power Optimized RNS Architecture for Security Based Applications Authors:G. ARCHANA KUMARI, R.SATHYAVENI |
0001-0004 |
Download | |
| IJVDCS 2 | Realization of Power Optimized Functional Broad Side Tests with BIST Sharing Logic Technique Authors:PINNAMARAJU SAHITYA, TANUJU SABBE |
0005-0011 |
Download | |
| IJVDCS 3 | A Low Power VDD Moduled SRAM Cell With Sense Amplifier Authors:P. GOWRI SWETHA, T. UMA MAHESWARI |
0012-0016 |
Download | |
| IJVDCS 4 | Adaptive Technique in Presenting of N×M-Bit RSFQ Multiplier For DSP/Multimedia Applications Authors:L. S. M. SINIKANTH, B. PRASANNA JYOTHI |
0017-0020 |
Download | |
| IJVDCS 5 | A Novel Approach to Implement Power Optimized PRPG for Fault Coverage Testing Applications Authors:ESWARI PANTHADI, M. SATEESH BABU |
0021-0025 |
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| IJVDCS 6 | Mapping of 4-Bit Array Multiplier using Cadence Tool for Low Power High Speed Authors:SUDHAKAR ALLURI, B. RAJENDRA NAIK, N. S. S. REDDY |
0026-0035 |
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| IJVDCS 7 | Parallel and Multiplier-Free Structures for Cyclic Convolution Based On the Improved F.O.M.A Authors:NAJEERUNNISA, P. RAVI KUMAR |
0036-0047 |
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| IJVDCS 8 | Real Time Implementation of Background Subtraction on FPGA Authors:K. BHARGAVI, G. SAMATHA |
0048-0053 |
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| IJVDCS 9 | Realization of Power Optimized CSDA for Video Compression Standards Authors:VADREVU SRILAKSHMI SRAVYA, MEDISETTY NAGENDRA KUMAR |
0054-0060 |
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| IJVDCS 10 | An Efficient Design of Reconfigurable FIR Filter Design for Memory Applications Authors:NENAVATH RAMESH, D.JYOTHI, DR. P. V. RAO |
0061-0067 |
Download | |
